Comments on: Quartus II Web-The Modern Way of Creating Electronic Systems Today

By: Albert van Bemmelen

Albert van Bemmelen — Mon, 15 May 2017 06:51:05 +0000

Glad you liked it Humberto! I've made another article were I also used the Tina designer program to test the repaired but still not correctly calibrated Exachron time pulse reciever with.

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By: Humberto

Humberto — Sat, 13 May 2017 05:36:37 +0000

Nice article Albert, I`ve really enjoyed reading it.

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By: Albert van Bemmelen

Albert van Bemmelen — Mon, 08 May 2017 16:24:51 +0000

Like Quartus other languages also support hierarchical structures. Like Java which supports hierarchical-inheritence. But there they are classes and not sub-circuits. Java also can have more than one sub class but only one super-class (Top-level hierarchy in Quartus). But Java is not a parallelprogramming language. There it matters where you put a command in a program, because it runs the Java code from top to bottom. After compiling. So not simultaneous.

Also the Tina designer program from Designsoft supports hierarchical structures in a parallel programming way. I recently started creating sub-circuits (called Macros in Tina) which afterwards can be given a component symbol (like in Quartus but with more options by using a special Tina Symbol designer program).
The best part is that it works both ways, you can make a Macro from any drawn circuit, but also design an empty Macro symbol and insert a VHDL circuit code to it to create your (sub-)circuit. But in case you want to make a VHDL conversion from your designed circuit it of course has to be a purely digital circuit! (VHDL simply doesn't support analogue components).

And the best part is that while creating very big top-level Macros (big higher hierarchy circuits), Tina supports an unlimited amount of these sub-circuits!

Creating is big fun in Tina and it supports simulation of both analogue and digital circuits (by using Scope Wave diagrams and other virtual measuring ways). Plus Mixed mode designing and simulation. Whereas Quartus is only capable of designing digital sub-circuits. Tina costs about 600 euro including the HDL software part. But that also depends on what version you buy. Quartus is free in its Web II/ Lite edition.

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By: Albert van Bemmelen

Albert van Bemmelen — Thu, 04 May 2017 06:37:43 +0000

PS: The majority vote vhdl code also can be written in the way as following code describes. Which also better explains how the higher Hierarchy files integrate the lower subcircuits in their VHDL code. And is in function exactly the same majority vote vhdl code as given in the article.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY majority_vote IS
port
(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
y : OUT STD_LOGIC
);
END majority_vote;

ARCHITECTURE bdf_type OF majority_vote IS

signal SYNTHESIZED_WIRE_0 : STD_LOGIC;
signal SYNTHESIZED_WIRE_1 : STD_LOGIC;
signal SYNTHESIZED_WIRE_2 : STD_LOGIC;

BEGIN

SYNTHESIZED_WIRE_2 <= a AND b;

SYNTHESIZED_WIRE_0 <= b AND c;

SYNTHESIZED_WIRE_1 <= a AND c;

y <= SYNTHESIZED_WIRE_0 OR SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2;

END;

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By: Albert van Bemmelen

Albert van Bemmelen — Thu, 04 May 2017 05:10:49 +0000

While comparing my old Quartus version 4.0 to new(er) version 13.1, I noticed that the RTL viewer was disabled in my old 4.0 version.
After checking by compiling my project 16_votes in newer version 13.1, it there was possible to use the RTL viewer in the free 13.1 version of Quartus II Web.
With the RTL viewer you can view your circuit as complete schematic and are able to check all subcircuits like Majority_vote, Two_votes etc.
The RTL viewer can be found in TOOLS => NETLIST VIEWER => RTL VIEWER. Which is also available in the free Xilinx ICE/Vivado program for Xilinx FPGAs.

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By: Albert van Bemmelen

Albert van Bemmelen — Wed, 03 May 2017 18:09:16 +0000

Thanks Robert!

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By: Robert Calk

Robert Calk — Wed, 03 May 2017 13:08:38 +0000

Nice job, Albert! Thanks for your great articles.

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By: Albert van Bemmelen

Albert van Bemmelen — Tue, 02 May 2017 16:17:25 +0000

In reply to Albert van Bemmelen.

Caused by not including all of the previous .bdf circuit files to the new and higher hierarchy circuit project. Which I thought would be already included by Quartus. Now all wrong .vwf generated diagrams are corrected and added to the article by Jestine today. Thanks for your help Paul!

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By: Albert van Bemmelen

Albert van Bemmelen — Tue, 02 May 2017 16:11:25 +0000

In reply to Albert van Bemmelen.

Now corrected!

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By: Albert van Bemmelen

Albert van Bemmelen — Tue, 02 May 2017 15:29:27 +0000

Jestine just made the corrections by replacing the wrong .vwf Vector Wave File diagrams by the correct ones I generated, after I eliminated the Project construction errors in the way as described in my post above. Only the Majority_vote (which is in this case 1_vote) diagram was correct before. So the diagrams for two_votes, four_votes and eight_votes are now corrected (my thanks to reader Paul who noticed it). I thought any new project build on a previous circuit .bdf file automatic would have all the lower Hierarchy files integrated. But they still all must be added by the user manually. Nowing this really anyone can start by programming electronic circuits in Quartus! It is easy, it is fun!!

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