Quartus II Web-The Modern Way of Creating Electronic Systems Today
After a few days, trying to simulate and compiling a circuit called “Majority_Vote” and producing a wave diagram in Quartus II Web designer I got the hang of it. Partly thanks to the amazing 1004 page’s thick book entitled “Digital Design with CPLD Applications and VHDL- by Robert Dueck 2nd Edition”. Which I can advise anyone! Information about starting with Quartus can be found from pages 200 and beyond. The CD-ROM with the book contains an old Quartus II Web version 4.0 that is great for slow PCs and notebooks, and a license is available free on-line after registration at Altera.
(The free license is temporary for 3-4 months but may not be easy updated in my version after pressing the Tools => License Setup => Web License Update extension because my version [2008?] was than a license-required version. Currently, Quartus II Web Free versions are completely free from Licenses. And I obtained my license through the Altera site at “Self Service Licensing” after specifying my unique laptop NIC code by email after the .dat License attachment from Altera could be added). I also used the free Xilinx Vivado software before but I like the Quartus software better.
My 1.6GHz old dual core Aspire 9411AWSMi 1.5GB Laptop was completely useless for current versions. All older versions are now followed by new version Quartus Pro and/or Prime Lite recently after Intel bought Altera for 16.7 Billion dollars and now is called Intel FPGA and SoC. That was also mainly the reason why it took me some time to begin. But version 90sp worked still fine. Nevertheless, I chose the CD-ROM version because I this way was sure that I could follow that book carefully. But keep in mind that older Quartus versions only support older FPGAs/CPLDs up to Cyclone III, whereas versions after Quartus II v13.1 support Cyclone IV FPGAs.
Below is the Majority_vote circuit we’ll use as first example:
The function of the circuit is to activate output y only on a majority of inputs (votes).
And that is exactly when output y becomes active (high) when at least 2 out of 3 votes are active.
- In Quartus, each circuit has the extension .bdf = block diagram / schematic file.
- Each wave chart after simulation has the extension .wvf = vector wave file.
- Each Quartus project extends the .qpf = quartus program file.
- And each symbol is the extension .bsf = block symbol file.
To create Simulation Waveforms we first open our circuit and compile it. Then open New => Other Files and choose Vector Waveform File. And with View => Utility Windows => Node Finder a new window opens that lists all our circuits connections. We simply select all our inputs and the one output by highlighing them and dragging them into our opened Simulation Waveforms window. And now may close our not needed Node Finder window afterwards. After we compile and/or press the Start Simulation button, if we already had compiled our circuit previously, the Simulation will start and if there were no faults show the Waveforms.
When we now create a new project consisting of 2 Majority circuits and call these Four_votes, output is high if there is a majority of votes for each Majority circuit. So 4 votes out of 6 which is a majority.
The circuit as said consisting of 2 Majority circuits looks the same as in the following two_votes.bdf screen. It is not necessary to draw the whole Majority circuit again twice to duplicate. Because we just make a symbol of the whole circuit that we can just add to the Quartus Library. We do this by creating a new project with the already named two_votes.
To do this, we add the circuit as a new symbol via “Create / Update => Create Symbol Files For Current File.” In the two_votes.bdf window we create in this project, we can open the Quartus symbol library and find the new symbol for the Majority circuit in the Map of Majority. Then we can simply stamp this symbol in the two_votes.bdf window. By choosing insert => symbol on the .bdf window. (by once clicking the mouse right button).
In the same way, inputs, outputs and ports can also be inserted in the two_votes window with the mouse pointer and clicking twice on the left mouse button. Each time the symbol library will open with the various schedule components. We must always save every step with File => Save As when we are done with our circuit, and usually the program promptly warns before we can take the next step.
Above the Wave diagram two_votes.wvf as result after simulation of the two_votes circuit. Here follows the VHDL generated code by Quartus II Web 4.0 code for the two_votes circuit:
======================================================================
— Copyright (C) 1991-2004 Altera Corporation
— PROGRAM “Quartus II”
— VERSION “Version 4.0 Build 190 1/28/2004 SJ Full Version”
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY two_votes IS
port
(
pin_name : IN STD_LOGIC;
pin_name3 : IN STD_LOGIC;
pin_name4 : IN STD_LOGIC;
pin_name5 : IN STD_LOGIC;
pin_name6 : IN STD_LOGIC;
pin_name7 : IN STD_LOGIC;
pin_name8 : OUT STD_LOGIC
);
END two_votes;
ARCHITECTURE bdf_type OF two_votes IS
component majority_vote
PORT(a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
y : OUT STD_LOGIC
);
end component;
signal SYNTHESIZED_WIRE_0 : STD_LOGIC;
signal SYNTHESIZED_WIRE_1 : STD_LOGIC;
BEGIN
b2v_inst : majority_vote
PORT MAP(a => pin_name,
b => pin_name3,
c => pin_name4,
y => SYNTHESIZED_WIRE_0);
b2v_inst1 : majority_vote
PORT MAP(a => pin_name5,
b => pin_name6,
c => pin_name7,
y => SYNTHESIZED_WIRE_1);
pin_name8 <= SYNTHESIZED_WIRE_0 AND SYNTHESIZED_WIRE_1;
END;
============================================================================
We can continue one step and design a four_votes circuit with the help of 2 two_votes circuits. To this end, we create a Symbol of the opened two_votes.bdf circuit.
This new four_votes which is actually a four majority voting circuit, follows below.
The circuit four_votes, is made of 2 two_votes circuits, or from 4 Majority circuits.
To prevent opening or overwriting the examples and excercitions as already included on the CD-ROM, I copied all examples to the Map C: / altera / qdesign and added the word orig to the original folder name of each individual chapter.
That way, I could be sure that I had completed the training correctly when making all the assignments myselves, instead of unintentionally, for example, having taken a .bsf symbol file from the original folder examples wrongly believing my excercise was successful. And my own folders got the same names as the original folders but were still completely empty.
The following Waveform .wvf file shows the result of the Four_votes Simulation:
And when Output y is not visible after simulation in the wvf window, it often helps choosing View => Fit in Window. Or by comparing the y output Count Value pulse time to those of the Inputs. (For example, when the Timing => At absolute times => Count every: 10.24 uS, and the y output is 10.00 uS, make it equal). It also helped to highlight all wave charts and then compile. But it is not clear why the wvf inputs and outputs do not always appear alike. This could easily be a bug in the old version of Quartus II Web 4.0. But if you get a second .vwf diagram opened over your first diagram you see that that one is the only correct one. And probably caused by a project error that was made. So check the Project wizard.
If you want to make a VHDL code of the circuit, that is very easily possible in Quartus. Entering a Circuit as HDL code instead of circuit blocks is also an option. (Choose Create / Update => Create HDL Design File for Current File, or Create AHDL Design File for Current File).
When we want to produce the circuit in VHDL code, we choose the HDL option and choose VHDL in the following screen. The file of our circuit in VHDL will then be written to the folder of the project as .vhd, and is then easily accessible with the explorer and notepad. Now, as an example, the result of the above-mentioned circuit in VHDL code is generated by the CD-ROM version Quartus II Web 4.0 provided by the aforementioned book 4.0:
==============================================================================
— Copyright (C) 1991-2004 Altera Corporation
— PROGRAM “Quartus II”
— VERSION “Version 4.0 Build 190 1/28/2004 SJ Full Version”
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY eight_votes IS
port
(
pin_name : IN STD_LOGIC;
pin_name2 : IN STD_LOGIC;
pin_name3 : IN STD_LOGIC;
pin_name4 : IN STD_LOGIC;
pin_name5 : IN STD_LOGIC;
pin_name6 : IN STD_LOGIC;
pin_name7 : IN STD_LOGIC;
pin_name8 : IN STD_LOGIC;
pin_name9 : IN STD_LOGIC;
pin_name10 : IN STD_LOGIC;
pin_name11 : IN STD_LOGIC;
pin_name12 : IN STD_LOGIC;
pin_name13 : OUT STD_LOGIC
);
END eight_votes;
ARCHITECTURE bdf_type OF eight_votes IS
component two_votes
PORT(a1 : IN STD_LOGIC;
b1 : IN STD_LOGIC;
c1 : IN STD_LOGIC;
a2 : IN STD_LOGIC;
b2 : IN STD_LOGIC;
c2 : IN STD_LOGIC;
y : OUT STD_LOGIC
);
end component;
signal SYNTHESIZED_WIRE_0 : STD_LOGIC;
signal SYNTHESIZED_WIRE_1 : STD_LOGIC;
BEGIN
b2v_inst : two_votes
PORT MAP(a1 => pin_name,
b1 => pin_name2,
c1 => pin_name3,
a2 => pin_name4,
b2 => pin_name5,
c2 => pin_name6,
y => SYNTHESIZED_WIRE_0);
b2v_inst1 : two_votes
PORT MAP(a1 => pin_name7,
b1 => pin_name8,
c1 => pin_name9,
a2 => pin_name10,
b2 => pin_name11,
c2 => pin_name12,
y => SYNTHESIZED_WIRE_1);
pin_name13 <= SYNTHESIZED_WIRE_0 AND SYNTHESIZED_WIRE_1;
END;
=================================================================================
After that I went on further than the book and I also made a 2 x eight_ vote circuit. This consists of a total of 8 Majority_vote circuits.
Here therefore, a majority applies to 2 of 3 times 8 = 16 votes of the total of 24 votes. Only then output y is 1.
For convenience, I’ve made all 24 inputs into one complete Group by highlighting them all and then adding a Value Count. (In this case, there are binary numbers from 0000000000000000000000 to 000111101000010001111111. And a total of 55255 transitions are executed.
Here follows the VHDL programming code of our 16_votes circuit consisting of 8 Majority circuits (2×8 majority circuit) :
=======================================================================
— Copyright (C) 1991-2004 Altera Corporation
— PROGRAM “Quartus II”
— VERSION “Version 4.0 Build 190 1/28/2004 SJ Full Version”
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY sixteen_votes IS
port
(
pin_name : IN STD_LOGIC;
pin_name3 : IN STD_LOGIC;
pin_name4 : IN STD_LOGIC;
pin_name5 : IN STD_LOGIC;
pin_name6 : IN STD_LOGIC;
pin_name7 : IN STD_LOGIC;
pin_name8 : IN STD_LOGIC;
pin_name9 : IN STD_LOGIC;
pin_name10 : IN STD_LOGIC;
pin_name11 : IN STD_LOGIC;
pin_name12 : IN STD_LOGIC;
pin_name13 : IN STD_LOGIC;
pin_name14 : IN STD_LOGIC;
pin_name15 : IN STD_LOGIC;
pin_name16 : IN STD_LOGIC;
pin_name17 : IN STD_LOGIC;
pin_name18 : IN STD_LOGIC;
pin_name19 : IN STD_LOGIC;
pin_name20 : IN STD_LOGIC;
pin_name21 : IN STD_LOGIC;
pin_name22 : IN STD_LOGIC;
pin_name23 : IN STD_LOGIC;
pin_name24 : IN STD_LOGIC;
pin_name25 : IN STD_LOGIC;
pin_name26 : OUT STD_LOGIC
);
END sixteen_votes;
ARCHITECTURE bdf_type OF sixteen_votes IS
component eight_votes
PORT(pin_name : IN STD_LOGIC;
pin_name2 : IN STD_LOGIC;
pin_name3 : IN STD_LOGIC;
pin_name4 : IN STD_LOGIC;
pin_name5 : IN STD_LOGIC;
pin_name6 : IN STD_LOGIC;
pin_name7 : IN STD_LOGIC;
pin_name8 : IN STD_LOGIC;
pin_name9 : IN STD_LOGIC;
pin_name10 : IN STD_LOGIC;
pin_name11 : IN STD_LOGIC;
pin_name12 : IN STD_LOGIC;
pin_name13 : OUT STD_LOGIC
);
end component;
signal SYNTHESIZED_WIRE_0 : STD_LOGIC;
signal SYNTHESIZED_WIRE_1 : STD_LOGIC;
BEGIN
b2v_inst : eight_votes
PORT MAP(pin_name => pin_name,
pin_name2 => pin_name3,
pin_name3 => pin_name4,
pin_name4 => pin_name5,
pin_name5 => pin_name6,
pin_name6 => pin_name7,
pin_name7 => pin_name8,
pin_name8 => pin_name9,
pin_name9 => pin_name10,
pin_name10 => pin_name11,
pin_name11 => pin_name12,
pin_name12 => pin_name13,
pin_name13 => SYNTHESIZED_WIRE_0);
b2v_inst1 : eight_votes
PORT MAP(pin_name => pin_name14,
pin_name2 => pin_name15,
pin_name3 => pin_name16,
pin_name4 => pin_name17,
pin_name5 => pin_name18,
pin_name6 => pin_name19,
pin_name7 => pin_name20,
pin_name8 => pin_name21,
pin_name9 => pin_name22,
pin_name10 => pin_name23,
pin_name11 => pin_name24,
pin_name12 => pin_name25,
pin_name13 => SYNTHESIZED_WIRE_1);
pin_name26 <= SYNTHESIZED_WIRE_0 AND SYNTHESIZED_WIRE_1;
END;
===========================================================================================
To understand how the Hierarchy of our circuit is build up, we simply can check this by opening our project view in the Compilation Hierarchy window named Entity on the left and click on our circuit name of our saved project to view our Hierarchy of circuits. See the screen picture Hierarchy above. As we can see that our TOP LEVEL circuit is called sixteen_votes. And that it in fact consist out of 8 (lowest level) majority_vote circuits. Because one majority_vote is 2 votes out of 3 and 8 times 2 is 16!
And here follows the 16_votes Vector Wave File diagram for the 16_votes .bdf circuit generated .vwf file:
Below is the base part of our structure in all of our VHDL codings (the base of our Hierarchy our Majority_vote circuit) :
============================================================================
ENTITY majority_vote IS
PORT(
a, b, c: IN BIT;
y : OUT BIT);
END majority_vote;
ARCHITECTURE maj_vote OF majority_vote IS
BEGIN
y <= (a and b) or (b and c) or (a and c);
END maj_vote;
=============================================================================
This shows the simplicity as well as the power of recording digital circuits in text (HDL).
With Quartus, we can easily enter (draw) as routine electronici, but also in VHDL and even in Verilog. Ideal, therefore, to teach programming a digital circuit in VHDL! All you need to do is draw your circuit and with the circuit on screen open Create/Update option in the File menu and pick the coding you want to proceed with. Of course after compiling your circuit first.
And so also ideal for all electronics beginners of these Jestine pages. FPGAs and CPLDs are the future and are all actually in place. They are super fast, cheap and can contain very complex circuits. For an introduction to VHDL programming see my previously published short article on that subject. There you can also read that each manufacturer has its own Jtag programmer, its own programming software and also has its own chips. But Altera, Xilinx and all other manufacturers have one thing in common: Their chips can all be programmed in VHDL or Verilog! And that it is a parallel programming language. Which means that each input, output or internal operation expires at the same time !!
The best part is that the software doesn’t cost a thing. The only obstacle could be the placing and soldering of our large to very large amount of FPGA chip pins on a circuit board. Which also means that because most of our circuit is in the chip instead on the board that our board can be very small in practice.
I think it was a enjoyable and most useful intro on working with Quartus II Web. And simply the modernest way of creating electronic systems today.
Albert van Bemmelen, Weert, The Netherlands
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https://jestineyong.com/automatic-solar-led-lights-repair/
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Parasuraman S
April 29, 2017 at 10:31 pm
Above my head!
Albert van Bemmelen
April 29, 2017 at 11:42 pm
Thank you Parasuraman S, I'm sure that if I can understand it, so can you. All you need to invest is some of your time. You do not even need the book, but it is certainly a big training and compendium for answering most of any questions you might have. I also needed a couple of days before I understood the Quartus program structure. Many Altera training guides can be found on-line. My article explains in short a couple of Quartus facts I didn't found in all of those documents. And although the version of Quartus II Web (4.0) I used is already very old, and probably can't be downloaded anymore from Altera's site, any old version still is great for entering the digital designing world. Today already versions 16.1 Prime Pro or Lite can be freely used and downloaded. But those versions require very Fast modern more Cpu core Personal Computers in order to Install and Run.
Albert van Bemmelen
April 30, 2017 at 12:57 am
Maybe it gets clearer when you read this. Since the VHDL code generated for Sixteen_votes and Eight_votes in the article is build on our Majority_vote circuit which is the base, only the .vhd code of Majority_vote has those primary Logic operator/functions. The higher level circuits based on it are (Top) Level hierarchy circuits that do not show those primary Boolean Logic functions but only mention the Majority_vote as being its base.
The higher level hierarchy circuits like our two_votes still mentions the two wires coming from both our two Majority Y outputs, in line y <= SYNTHESIZED_WIRE_0 AND SYNTHESIZED_WIRE_1;
This will be completely clear if you also compile the base Majority_vote file into a .vhd file and study it. And the Hierarchy of any created project file can be seen at the upper left window with name Entity. If you select there Hierarchy the Entity window will show your project name and its structure.
Paul Kellahan
April 30, 2017 at 6:59 am
Hi Albert,
I have enjoyed reading your posts over the years that I have been subscribed. I love the enthusiasm that you put into your work, research and writing.
There is a problem with the output you have for the two_votes2.vwf that you provided. The output y is exactly the same as input c1 which means that the overall equation is simply y=c1 not a majority but a dictatorship 😉
The output should have a high output whenever there are 2 or 3 high inputs in both upper and lower sets according to the diagram in two_votes.bdf
Maybe you have posted the wrong output since the file base names are different?
The expansion of the 3 input majority_vote circuit using an AND gate produces a "majority of majorities" circuit. (Like a referendum where you need a majority of voters in a majority of States to pass not an overall majority)
To get a 6 input true majority vote circuit you need to have (as far as I remember) six times 5 input AND gates for the inputs, all interconnected and becomes ever more complex as the number of inputs increases.
I am not sure how you would increase the design modularly. Perhaps something similar to the overflow output in a full adder circuit which cascades to the next module.
Paul Kellahan
May 1, 2017 at 5:36 am
Correction: The "majority of majorities" circuit would have three majority_vote modules feeding the inputs of a fourth to produce the output. This gives nine voting inputs with 4 out of 9 being the minimum to get a high output but they need to be 2 each from 2 different input groups. Like a referendum.
Suranga Electronics
April 30, 2017 at 11:24 am
Mr.Albert. Great and very important article but a little bit complicated to me. Anyway, thanks.
Albert van Bemmelen
May 2, 2017 at 11:48 am
Thank you Mr.Suranga, it is and looks complicated stuff at first! But with Quartus (or with other software like Xilinx's also Free ICE WebPACK/Vivado for Linux and Windows OS), it becomes much simpler, and how and why to use it. Because it also is great stuff! Although I for some reason had generated the wrong .vwf vector wave(s) after the Majority circuit which I have corrected and send in afterwards. And I leave it up to Jestine to correct the article or to publish my new send in article to replace it. So the text and presented .vhdl code is okay but the two_votes and following .vwf (Vector Wave Files) that were simulated from the circuits are mistakenly the wrong generated pictures. Paul in the post above noticed it. I am still figuring out how that so called 'bug' happened, although I know how to generate the right vector waves. It is just a matter of checking the results, and finding those hidden project errors.
Albert van Bemmelen
May 3, 2017 at 12:11 am
Now corrected!
Albert van Bemmelen
April 30, 2017 at 5:04 pm
Thank you Paul. Let me try to answer your questions, because I certainly do not claim to be an expert here and maybe already my above post answers most of your questions. I guess that this is the case if both posts showed up today simultaneous and you probably had uploaded your post before reading mine?
The presented vhdl code for Eight_votes (4 majority circuits) and Sixteen_votes (8 majority circuits) were exactly as given generated by Quartus II Web 4.0.
So I do not think there was anything wrong with them.
Of course you are right to state that 2 out of 3 is a majority, and when doubled so is 4 out of 6. When again doubled to 12 voters, 8 is only still 2/3 of 12 votes like before, but now already 7 votes would be a majority.
Only for simplicity and to be able to show how to duplicate a circuit in Quartus into a bigger new circuit we assumed that 2/3 always was the majority of votes. I didn't look how to increase the design further into a correct majority voting system because that would have made it difficult to show how to make a library symbol of any correctly compiled digital circuit. New Quartus programming information on the subject of creating digital circuits you might have is greatly appreciated!
Albert van Bemmelen
April 30, 2017 at 10:52 pm
About y being generated out of two majority votes meaning group a1,b1,c1 AND
group a2,b2,c2 both must have a majority vote simultaneous, indeed gives the wrong .wvf two_votes diagram in Quartus, Paul. I didn't notice it. It seems that generating the y value out of the input waves is going wrong somewhere in my program. That must the bug in my Quartus II Web 4.0 version I spoke about in the article. I grouped both a1,b1,c1 and assigned a Value Count to them, and the same goes for group a2,b2,c2. So that can't be it. I do not know why that happened? Any ideas why compiling my circuit gave no error at all, but still simulating the wavediagrams as a result keep on being wrong although there was no single error reported?
Albert van Bemmelen
May 3, 2017 at 12:17 am
Caused by not including all of the previous .bdf circuit files to the new and higher hierarchy circuit project. Which I thought would be already included by Quartus. Now all wrong .vwf generated diagrams are corrected and added to the article by Jestine today. Thanks for your help Paul!
Albert van Bemmelen
April 30, 2017 at 11:33 pm
I just repeated the project two_votes and I found what caused the simulation error, and probably the bug I mentioned in the article, Paul.
It wasn't the compiling or the simulation itself that caused it. Because there were no errors reported. But it must have been caused by saving and or overwriting the Project File and/or Vector Waveform File incorrectly, or the wrong file. I will check my Simulation better next time. Thanks Paul!
When studying we mustn't give up so quickly and keep on going where we left off. I was so enthousiastic about Quartus I didn't notice the errors. After all said and done, following tekst came to mind "We never give up, we never surrender!", from the great and funny SF movie Space Quest 1999. (LOL).
Albert van Bemmelen
May 1, 2017 at 2:38 pm
Yesterday I was curious how Quartus II Web version 13.1 (32-bit) would function.
I noticed it didn't accept my quad-core PC because the free version only allows 1 cpu core. But it detect my 4 core cpu. Which doesn't make version 13.1 any faster than my old version 4.0 sadly. Also Parallel compilation is not licensed and so disabled. And although much in the 13.1 menu still is the same compared to the old 4.0 version, I noticed that the .vwf Simulator window now opens in a separate popup screen. And also the Nodes (inputs & output pins of our circuit) can not easily be dragged into our Vector Waveform window like before. Although in the Quartus main window there still is the old "Utility Windows => Node Finder", but that doesn't work the Selecting and Dragging way anymore because of the new Vector Waveform popupscreen that has its own Node Finder integrated. Somehow I think the old version not only was much faster but also much more intuitive. Somehow only just opening 1 new project file produces the correct Vector Wave diagram in the Simulator. Continuing with a higher hierarchy circuit in a new project (bigger circuit made from smaller circuit parts like the Majority_votes circuit) corrupts my Output results. And that is something that is very unclear in Quartus, although there were no errors in the previous circuit it was made of after compiling it.
Albert van Bemmelen
May 2, 2017 at 3:04 pm
It now is completely clear why some wrong .vwf Vector Wave File diagrams were generated. The issue simply occurs when, while creating a higher hierarchy circuit (made of smaller previously made circuit .bdf files), not all previous .bdf files were included. So simply by adding those to for instance my 16 votes circuit project, it would mean that the .bdf files majority vote, two votes, four votes and the eight votes files need to be included. After that the results will be correct and the simulation .vwf won´t for instance popup twice. You can add those files when you create a new project or afterwards by the menu option Project =>`Add Remove Files in Project. Quartus is really great!!
Albert van Bemmelen
May 2, 2017 at 11:29 pm
Jestine just made the corrections by replacing the wrong .vwf Vector Wave File diagrams by the correct ones I generated, after I eliminated the Project construction errors in the way as described in my post above. Only the Majority_vote (which is in this case 1_vote) diagram was correct before. So the diagrams for two_votes, four_votes and eight_votes are now corrected (my thanks to reader Paul who noticed it). I thought any new project build on a previous circuit .bdf file automatic would have all the lower Hierarchy files integrated. But they still all must be added by the user manually. Nowing this really anyone can start by programming electronic circuits in Quartus! It is easy, it is fun!!
Robert Calk
May 3, 2017 at 9:08 pm
Nice job, Albert! Thanks for your great articles.
Albert van Bemmelen
May 4, 2017 at 2:09 am
Thanks Robert!
Albert van Bemmelen
May 4, 2017 at 1:10 pm
While comparing my old Quartus version 4.0 to new(er) version 13.1, I noticed that the RTL viewer was disabled in my old 4.0 version.
After checking by compiling my project 16_votes in newer version 13.1, it there was possible to use the RTL viewer in the free 13.1 version of Quartus II Web.
With the RTL viewer you can view your circuit as complete schematic and are able to check all subcircuits like Majority_vote, Two_votes etc.
The RTL viewer can be found in TOOLS => NETLIST VIEWER => RTL VIEWER. Which is also available in the free Xilinx ICE/Vivado program for Xilinx FPGAs.
Albert van Bemmelen
May 4, 2017 at 2:37 pm
PS: The majority vote vhdl code also can be written in the way as following code describes. Which also better explains how the higher Hierarchy files integrate the lower subcircuits in their VHDL code. And is in function exactly the same majority vote vhdl code as given in the article.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY majority_vote IS
port
(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
y : OUT STD_LOGIC
);
END majority_vote;
ARCHITECTURE bdf_type OF majority_vote IS
signal SYNTHESIZED_WIRE_0 : STD_LOGIC;
signal SYNTHESIZED_WIRE_1 : STD_LOGIC;
signal SYNTHESIZED_WIRE_2 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_2 <= a AND b;
SYNTHESIZED_WIRE_0 <= b AND c;
SYNTHESIZED_WIRE_1 <= a AND c;
y <= SYNTHESIZED_WIRE_0 OR SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2;
END;
Albert van Bemmelen
May 9, 2017 at 12:24 am
Like Quartus other languages also support hierarchical structures. Like Java which supports hierarchical-inheritence. But there they are classes and not sub-circuits. Java also can have more than one sub class but only one super-class (Top-level hierarchy in Quartus). But Java is not a parallelprogramming language. There it matters where you put a command in a program, because it runs the Java code from top to bottom. After compiling. So not simultaneous.
Also the Tina designer program from Designsoft supports hierarchical structures in a parallel programming way. I recently started creating sub-circuits (called Macros in Tina) which afterwards can be given a component symbol (like in Quartus but with more options by using a special Tina Symbol designer program).
The best part is that it works both ways, you can make a Macro from any drawn circuit, but also design an empty Macro symbol and insert a VHDL circuit code to it to create your (sub-)circuit. But in case you want to make a VHDL conversion from your designed circuit it of course has to be a purely digital circuit! (VHDL simply doesn't support analogue components).
And the best part is that while creating very big top-level Macros (big higher hierarchy circuits), Tina supports an unlimited amount of these sub-circuits!
Creating is big fun in Tina and it supports simulation of both analogue and digital circuits (by using Scope Wave diagrams and other virtual measuring ways). Plus Mixed mode designing and simulation. Whereas Quartus is only capable of designing digital sub-circuits. Tina costs about 600 euro including the HDL software part. But that also depends on what version you buy. Quartus is free in its Web II/ Lite edition.
Humberto
May 13, 2017 at 1:36 pm
Nice article Albert, I`ve really enjoyed reading it.
Albert van Bemmelen
May 15, 2017 at 2:51 pm
Glad you liked it Humberto! I've made another article were I also used the Tina designer program to test the repaired but still not correctly calibrated Exachron time pulse reciever with.